- July 2016
- First demonstration of crossbar RRAM for conv operation
1T1R Array (128x64) for Convolutional Layer
https://www.nature.com/articles/s41928-017-0002-z?WT.feed_name=subjects_engineering
https://www.nature.com/articles/s41928-017-0002-z?WT.feed_name=subjects_engineering
- Dec. 2017
- First demonstration of 1T1R array for conv operation
- Jan. 2020
- Off-chip ARM core for ReLU
- 11,041 GOPS/W with 96% accuracy on MNIST
1T1R Array for Ternary Weights Binary Inputs CNN
- Aug. 2019
- FPGA for controller, activation function and pooling
- 16.95 TOPS/W with 97% accuracy on MNIST
1T1R Array (Eight 256x512 Arrays) for Multibit Input, Weight and Output CNN
- Jan. 2020
- 2-bit input, 3-bit weight and 4-bit output
- 53.17 TOPS/W for 1-bit input
- 21.9 TOPS/W for 2-bit input
- Accumulation parallelism: 9
1T1R Array (Eight 512x512 Arrays) for Multibit Input, Weight and Output CNN
- Feb. 2020
- 2-bit input, 4-bit-weight and 10-bit output
- 45.52 TOPS/W
- Accumulation parallelism: 16
1T1R Array (48 256x256 Arrays) for Multibit Input, Weight and Output CNN
- Aug. 2022
- Use voltage-mode sensing instead of current-mode sensing
- 8-bit input, 4-bit-weight and 10-bit output
- 43 TOPS/W for 1-bit input
- 40 TOPS/W for 2-bit input
- 16 TOPS/W for 4-bit input
- 7 TOPS/W for 8-bit input
- Accumulation parallelism: 256
Reference Survey Paper
